x86 debugging scrutinies
category: code [glöplog]
I used Turbo Debugger too see how the cpu-flags are affected and I can't get my head around the following:
According to the Intel Manuals and docs I've read online the zero-flag is not affected after a MUL/IMUL etc, but Turbo Debugger shows something completely different.
What am I missing? Does the z-flag get set, when result in AX=0 ? is that what happens? but why does the docs say zeroflag is not affected?
Here shows the zero-flag status is changed to '1' after MUL (btw the example code shown are from tuk-tuk.com by frag):
According to the Intel Manuals and docs I've read online the zero-flag is not affected after a MUL/IMUL etc, but Turbo Debugger shows something completely different.
What am I missing? Does the z-flag get set, when result in AX=0 ? is that what happens? but why does the docs say zeroflag is not affected?
Here shows the zero-flag status is changed to '1' after MUL (btw the example code shown are from tuk-tuk.com by frag):
just to quote:
Quote:
MUL—Unsigned Multiply
...
Flags Affected
The OF and CF flags are set to 0 if the upper half of the result is 0; otherwise, they are set to 1. The SF, ZF, AF, and PF flags are undefined.
I missed the undefined part..
It might be a good idea to check stuff like that on your real CPU instead of in an emulator that may or may not follow Intel manuals.
or many cpu's if it's undefined behavior
ZF reflects the IMUL result on my old Atom, but AMDs don't set it.
My docs say that CF/OF are predictable, SF/ZF/AF/PF are not.
(This was an issue on this year's Function :D)
My docs say that CF/OF are predictable, SF/ZF/AF/PF are not.
(This was an issue on this year's Function :D)
By the way, the CF/OF triggers allow for a beautiful optimization - together with the 0xCCCD trick, and with reusing the "0x10" of "int 0x10" =)
Sizecoding Wiki
I'd rather not rely on the other flags though ;)
Quote:
Like before the mul di instruction triggers the overflow flag - and the carry flag - always but twice per frame. CL remains 0xFF unchanged from start, so adc [bp+si],cl effectively decrements the framecounter twice per frame.
Sizecoding Wiki
I'd rather not rely on the other flags though ;)
There's an interesting trick to determine CPU vendor (Intel or AMD):
Code:
xor dx,dx ; zf = 0
div sp ; or any other reg that <> 0
jnz .AMD ; on any div/idiv operation ZF flag will not be changed on Intel but will be set on AMD
.Intel:
*sorry, will be cleared on AMD :)
See here: undefined integer FLAGS behavior
And here for more discussion (including peterferrie's interesting explanation of "undefined")...
And here for more discussion (including peterferrie's interesting explanation of "undefined")...
Oh great, there is somebody else using Turbo Assembler!
