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x86 debugging scrutinies

category: code [glöplog]
 
I used Turbo Debugger too see how the cpu-flags are affected and I can't get my head around the following:

According to the Intel Manuals and docs I've read online the zero-flag is not affected after a MUL/IMUL etc, but Turbo Debugger shows something completely different.

What am I missing? Does the z-flag get set, when result in AX=0 ? is that what happens? but why does the docs say zeroflag is not affected?

Here shows the zero-flag status is changed to '1' after MUL (btw the example code shown are from tuk-tuk.com by frag):

BB Image
added on the 2016-09-27 16:33:22 by rudi rudi
just to quote:
Quote:

MUL—Unsigned Multiply
...
Flags Affected

The OF and CF flags are set to 0 if the upper half of the result is 0; otherwise, they are set to 1. The SF, ZF, AF, and PF flags are undefined.
added on the 2016-09-27 16:36:16 by rudi rudi
I missed the undefined part..
added on the 2016-09-27 16:36:58 by rudi rudi
It might be a good idea to check stuff like that on your real CPU instead of in an emulator that may or may not follow Intel manuals.
added on the 2016-09-27 21:33:10 by absence absence
or many cpu's if it's undefined behavior
added on the 2016-09-27 23:38:07 by ferris ferris
ZF reflects the IMUL result on my old Atom, but AMDs don't set it.
My docs say that CF/OF are predictable, SF/ZF/AF/PF are not.
(This was an issue on this year's Function :D)
added on the 2016-09-29 14:09:32 by rrrola rrrola
By the way, the CF/OF triggers allow for a beautiful optimization - together with the 0xCCCD trick, and with reusing the "0x10" of "int 0x10" =)
Quote:
Like before the mul di instruction triggers the overflow flag - and the carry flag - always but twice per frame. CL remains 0xFF unchanged from start, so adc [bp+si],cl effectively decrements the framecounter twice per frame.


Sizecoding Wiki

I'd rather not rely on the other flags though ;)
added on the 2016-09-29 14:32:38 by HellMood HellMood
There's an interesting trick to determine CPU vendor (Intel or AMD):
Code: xor dx,dx ; zf = 0 div sp ; or any other reg that <> 0 jnz .AMD ; on any div/idiv operation ZF flag will not be changed on Intel but will be set on AMD .Intel:
added on the 2022-02-21 19:21:19 by Jin X Jin X
*sorry, will be cleared on AMD :)
added on the 2022-02-21 19:32:12 by Jin X Jin X
See here: undefined integer FLAGS behavior

And here for more discussion (including peterferrie's interesting explanation of "undefined")...
added on the 2022-02-21 20:26:25 by VileR VileR
Oh great, there is somebody else using Turbo Assembler!
added on the 2022-02-22 08:13:28 by rac rac

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