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category: code [glöplog]
clr.w -(sp)
trap #1
added on the 2024-05-31 14:54:13 by gloky gloky
lda split_table, x
sta $d012
added on the 2024-06-05 13:08:49 by Preacher Preacher
Code: ldh a,[rLY] rra and %01111100 ldh [rBGPD],a
added on the 2024-06-08 06:10:32 by DevEd DevEd
Code: db $64,$66,$0f,$bf,$15 {movsx edx, fs:[di]} {v.x} @n_plan_x2: db $66,$69,$d2, $00,$00,$00,$00 {imul edx, n_plan.x}
added on the 2024-06-08 06:52:22 by bitl bitl
; really porky and fast coded code
.ins
SF D0
TST.b D0 ; not sure if necessary
BEQ.S .P0
.P1
move.l adrpatern,a1
bra.s .titi
.P0
move.l adrpatern+4,a1
.titi
eor.w #$0100,.ins ; transform sf into st and vice versa

; result is alternate value of adrpatern or adrpatern+4 in a1
lea .retour,a6
movem.w (a1)+,d0-d6/a2-a4
jmp (a5)
.retour
added on the 2024-06-11 04:31:59 by gloky gloky
Code: case USB_HEADER_CALL_ACTION: { // Function addresses are on PROG(R) : origin = 0x3F8080, length = 0x1F80 // So the address is coded on the last 15 bits and 0x003F8000 is added. int32_t address = 0x003F8000 + USB_Read16(); int16_t sizeIn = USB_Read8(); switch(sizeIn) { case 0x00: ((void (*)(void)) address)(); break; case 0x02: ((void (*)(int16_t)) address)(USB_Read16()); break; case 0x04: ((void (*)(int32_t)) address)(USB_Read32()); break; case 0x22: ((void (*)(int16_t, int16_t)) address)(USB_Read16(), USB_Read16()); break; case 0x24: ((void (*)(int16_t, int32_t)) address)(USB_Read16(), USB_Read32()); break; } } break;
added on the 2024-06-11 14:41:17 by Orace Orace
Code: case 0x9Eu: // arc
added on the 2024-06-12 00:15:23 by bsp bsp
Code: [18, "yourmom", "in"], [21, "yourmom", "out"],
added on the 2024-06-20 16:52:13 by immibis immibis
Code:char *number_ret = malloc((size_t)floor(log10((double)INT64_MAX)));
added on the 2024-06-20 18:36:03 by Funkstill Funkstill
Quote:
; really porky and fast coded code
.ins
SF D0
TST.b D0 ; not sure if necessary
BEQ.S .P0
.P1


The tst.b instruction is necessary, sf and friends do not set any flags.
added on the 2024-06-20 20:32:25 by StingRay StingRay
Code: *=$1000 init tax clrreg sta $d400,x inx bne clrreg lda #$0f sta $d418 sta $d400 sta $d413 lda #$f8 sta $d406 lda #$ed sta $d40c nopl dec play+1 rts play lda #$02 bne nopl lda #$02 sta play+1 trr lda #$00 bne pll lda #$80 sta trr+1 asl sta $d40b sta $d412 tr ldx #$00 cpx #$04 bne trk lda v3b+1 eor #%01100000 sta v3b+1 inc count+1 ldx #$00 stx tr+1 trk lda tra,x sta tran+1 inc tr+1 pll dec trr+1 pl ldx #$07 lda inst,x sta $d404 bne instok lda #$08 sta pl+1 instok dec pl+1 lda tra,x cmp #$04 bne drm clc tran adc #$04 drm sta $d401 clc adc #$04 sta $d408 v3 lda #$00 v3b and #%00011111 sta $d40f lda #$55 sta $d40b count lda #$00 cmp #$02 beq v31 cmp #$03 beq v32 cmp #$04 beq v33 cmp #$05 beq v33 cmp #$06 beq v34 rts v31 lda #$13 sta $d412 dec v3+1 rts v32 lda #$17 sta $d412 rts v33 lda #$17 sta $d412 bne *-15 v34 lda #$00 sta count+1 rts inst .byte $00,$81,$10,$81,$20,$21,$11,$51 tra .byte $00,$08,$0a,$0c,$00,$04,$04,$04
added on the 2024-06-20 22:04:02 by mermaid mermaid
sta <VIA_t1_cnt_lo
added on the 2024-06-21 16:22:41 by Fell Fell
POKE 788,82 ; C64
added on the 2024-06-23 19:49:32 by MrVainSCL MrVainSCL

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